DESIGN AND ANALYSIS OF 4:1 MULTIPLEXER USING AN EFFICIENT REVERSIBLE LOGIC IN 180nm

Multiplexer’s square measure is a typical building block for data-paths, and is used extensively in a variety of applications together with the processors. In this paper authors have proposed a 4:1 multiplexer using PFAL and ECRL adiabatic logic design technique and compared with the Conventional CMOS Multiplexer. The basic approaches that we used for reducing energy/power dissipation in conventional CMOS circuits include varying the rise time and full time, on decreasing frequency and minimize the switching activities with efficient charge recovery logic. The Adiabatic switching technique based upon the energy recovery principle is one of the techniques which is widely used to achieve low power VLSI design circuits. In the following paper, the power dissipation of various adiabatic circuits is calculated and then simulated using TANNER